/*********************************************************************
							
	File: top_de115.v 
	
	Copyright (C) 2013  Alireza Monemi

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
	
	
	Purpose:
	The top module for DE2-115 Altra board

	Info: monemi@fkegraduate.utm.my

****************************************************************/




`include "define.v"
module top_de115 #(
	parameter VC_NUM_PER_PORT 			=	`VC_NUM_PER_PORT_DEF,
	parameter PYLD_WIDTH 				=	`PYLD_WIDTH_DEF,
	parameter BUFFER_NUM_PER_VC		=	`BUFFER_NUM_PER_VC_DEF,
	parameter X_NODE_NUM					=	`X_NODE_NUM_DEF,
	parameter Y_NODE_NUM					=	`Y_NODE_NUM_DEF,
	
	parameter FLIT_TYPE_WIDTH			=	2,
	parameter PORT_NUM					=	5,
	parameter NIOS_RAM_WIDTH			=	13,
	parameter S_ADDR_SIZE				=	2,
	parameter SW_OUTPUT_REGISTERED	=	0,// 1: registered , 0 not registered
	parameter CMD_RAM_ADDR_WIDTH		=	5,
	parameter COD_RAM_ADDR_WIDTH		=	8,
	parameter CAND_VC_SEL_MODE			=	0,
	
	parameter SDRAM_EN					=	1,//  0 : disabled  1: enabled 
	parameter SDRAM_ADDR_WIDTH			=	25,
	parameter SDRAM_SW_X_ADDR			=	1,
	parameter SDRAM_SW_Y_ADDR			=	0,
	parameter SDRAM_NIC_CONNECT_PORT	=	0, // if topology is star over mesh and the router is edge router it can be  connected to other port 
	
	parameter JTAG_INTERFACE_EN		=	1, // if disabled the jtag can just send packet but can not recieve any packet
	parameter JTAG_SW_X_ADDR			=	0,
	parameter JTAG_SW_Y_ADDR			=	0,
	parameter JTAG_NIC_CONNECT_PORT	=	0,
	parameter TOTAL_ROUTERS_NUM		=	X_NODE_NUM		* Y_NODE_NUM
)
(


		input 												CLOCK_50,
		input		[1								:	0]		KEY,
		output	[2								:	0]		LEDG,
		output	[TOTAL_ROUTERS_NUM-1		:	0]		LEDR,
		
		// DRAM interface
		output 	[12							:	0]		DRAM_ADDR,
		output	[1								:	0]		DRAM_BA,
		output												DRAM_CAS_N,
		output												DRAM_CKE,
		output												DRAM_CLK,
		output												DRAM_CS_N,
		inout		[31							:	0]		DRAM_DQ,
		output	[3								:	0]		DRAM_DQM,		
		output												DRAM_RAS_N,
		output												DRAM_WE_N
);
	
	


	wire													reset;
	wire													nios_reset;
	wire													clk;
	wire	[TOTAL_ROUTERS_NUM-1			:0]		led;
	wire													jtag_led;
	
	

	assign 	clk		=	CLOCK_50;
	assign 	LEDR		=	led;
	assign	LEDG[0]	=	nios_reset;
	assign	LEDG[1]	=	reset;
	assign	LEDG[2]	=	jtag_led;
	assign	reset		=	~KEY[0];

mpsoc #(

	.VC_NUM_PER_PORT			(VC_NUM_PER_PORT),
	.PYLD_WIDTH 				(PYLD_WIDTH),
	.BUFFER_NUM_PER_VC		(BUFFER_NUM_PER_VC),
	.FLIT_TYPE_WIDTH			(FLIT_TYPE_WIDTH),
	.PORT_NUM					(PORT_NUM),
	.X_NODE_NUM					(X_NODE_NUM),
	.Y_NODE_NUM					(Y_NODE_NUM),
	.NIOS_RAM_WIDTH			(NIOS_RAM_WIDTH),
	.S_ADDR_SIZE				(S_ADDR_SIZE),
	.CMD_RAM_ADDR_WIDTH		(CMD_RAM_ADDR_WIDTH),
	.COD_RAM_ADDR_WIDTH		(COD_RAM_ADDR_WIDTH),
	.SDRAM_EN					(SDRAM_EN),//  0 : disabled  1: enabled 
	.SDRAM_SW_X_ADDR			(SDRAM_SW_X_ADDR),
	.SDRAM_SW_Y_ADDR			(SDRAM_SW_Y_ADDR),
	.SDRAM_NIC_CONNECT_PORT	(SDRAM_NIC_CONNECT_PORT	), // if topology is star over mesh and the router is edge router it can be  connected to other port 
	.SW_OUTPUT_REGISTERED	(SW_OUTPUT_REGISTERED),// 1: registered , 0 not registered
	.SDRAM_ADDR_WIDTH			(SDRAM_ADDR_WIDTH),
	.CAND_VC_SEL_MODE			(CAND_VC_SEL_MODE),
	
	.JTAG_INTERFACE_EN		(JTAG_INTERFACE_EN), // if disabled the jtag can just send packet but can not recieve any packet
	.JTAG_SW_X_ADDR			(JTAG_SW_X_ADDR),
	.JTAG_SW_Y_ADDR			(JTAG_SW_Y_ADDR),
	.JTAG_NIC_CONNECT_PORT	(JTAG_NIC_CONNECT_PORT)
		
)
the_mpsoc
(
	.reset						(reset),
	.nios_reset					(nios_reset),
	.clk							(clk),
	.led							(led),
	.jtag_led					(jtag_led),
	
	.sdram_addr					(DRAM_ADDR),        // sdram_wire.addr
	.sdram_ba					(DRAM_BA),          //           .ba
	.sdram_cas_n				(DRAM_CAS_N),       //           .cas_n
	.sdram_cke					(DRAM_CKE),         //           .cke
	.sdram_cs_n					(DRAM_CS_N),        //           .cs_n
	.sdram_dq					(DRAM_DQ),          //           .dq
	.sdram_dqm					(DRAM_DQM),         //           .dqm
	.sdram_ras_n				(DRAM_RAS_N),       //           .ras_n
	.sdram_we_n					(DRAM_WE_N),        //           .we_n
	.sdram_clk					(DRAM_CLK)		    	//  sdram_clk.clk
	
);




endmodule
